1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and, more particularly, to a global column select structure for accessing a memory, such as a dynamic random access memory (DRAM), for example.
2. Description of the Related Art
Modern integrated circuit memory devices generally include high density memory arrays on an integrated circuit chip. The array contains many memory cells, each of which stores a bit of data. In many memory devices, such as dynamic random access memories (DRAMs), for example, each of the memory cells stores an electrical charge, where the value of the electrical charge is indicative of the logical bit value stored in the cell. The absence of an electrical charge in the memory cell may indicate a logical “zero;” whereas, the presence of an electrical charge in the memory cell may indicate a logical “one.”
The numerous memory cells in an integrated circuit memory device are typically arranged in an array having a number of intersecting rows and columns. One memory cell is normally associated with each intersection of a row and a column. Word lines, which correspond to rows in the array, are used to access the memory cells connected to that word line. Bit lines, which correspond to columns in the array, are used to interconnect memory cells to sense amplifiers where the presence or absence of an electrical charge in the memory cell can be detected. Row decoders and column decoders activate a selected word line and a selected bit line to access a particular memory cell as designated by an address input to the memory device.
Typically, the various columns of the memory array are grouped into sub arrays. Data within these columns is retrieved by either a column select (CS) bit line or a global column select (GCS) bit line that is routed from a periphery of the integrated circuit chip to the memory array. Generally, the CS bit line is used to address a particular sense amplifier to select from a column of data within a “local” sub array. The GCS bit line, on the other hand, is used to “globally” select from particular columns of data from the sub arrays. Typically, the CS bit line is routed from the periphery of the integrated circuit chip to the memory array through an intermediate layer that separates an upper data storage (e.g., capacitive) layer and a lower logic layer that forms the memory array. The GCS bit line is typically routed above the data storage layer (i.e., above the memory array) between the periphery of the integrated circuit chip and the memory array.
It is generally desired in device designs incorporating PCRAM operation, for example, to have the area over the data storage layer (i.e., the memory array) free of any patterning to allow for cell definition. Because the GCS bit line is typically routed over the memory array, the area over the array is not substantially free, which may make PCRAM operation difficult (i.e., it is desirable to form PCRAM memory cell materials as a continuous sheet). Additionally, because the height of the data storage layer is typically on an order of three times the height of the logic layer, routing the GCS bit line over the data storage layer yields a very deep via that must be etched in the integrated circuit chip to route the GCS line down to the substrate of the chip. For example, the via could be as much as 3 microns deep, which is highly undesirable when 0.1-0.15 micron design constraints are typically contemplated.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.